Author:
Finlayson I.,Gang-Ryung Uh ,Whalley D.,Tyson G.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Hardware and Architecture
Cited by
8 articles.
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1. Design and Implementation of Five Stages Piplined RISC Processor on FPGA;2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA);2023-05-21
2. An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications;Microprocessors and Microsystems;2020-03
3. Optimizing Transfers of Control in the Static Pipeline Architecture;ACM SIGPLAN Notices;2015-07-22
4. Optimizing Transfers of Control in the Static Pipeline Architecture;Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM;2015-06-04
5. A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor;Journal of Signal Processing Systems;2014-09-28