Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS
Author:
Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/7994/22113/01029505.pdf?arnumber=1029505
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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4. Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities;Minimizing and Exploiting Leakage in VLSI Design;2009-10-20
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