Hybrid on-line self-test architecture for computational units on embedded processor cores-Reference-Cited by-同舟云学术

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Hybrid on-line self-test architecture for computational units on embedded processor cores

Published:2019-04 Issue: Volume: Page:
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Container-title:2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
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Author:

Floridia Andrea,Mongano Gianmarco,Piumatti Davide,Sanchez Ernesto

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8718445/8724630/08724647.pdf?arnumber=8724647

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low Power Consumption Online Testing Technique for Wearable Wireless Body Area Networks;2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS);2022-11-16

2. A Low-cost BIST Design Supporting Offline and Online Tests;Journal of Electronic Testing;2022-02

3. Structural sparsity in control design of active and semi‐active systems;Structural Control and Health Monitoring;2021-04-28

4. Integrating Online Safety-related Memory Tests in Multicore Real-Time Systems;2020 IEEE Real-Time Systems Symposium (RTSS);2020-12

5. Test and Diagnosis Solution for Functional Safety;2020 IEEE International Test Conference (ITC);2020-11-01

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