Benchmarking for Hardware Security: Types, Design Levels, and Limitations
Author:
Affiliation:
1. Wright state university,Computer science and engineering,Dayton,United states
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10405424/10405847/10405976.pdf?arnumber=10405976
Reference32 articles.
1. ENCIDER: Detecting Timing and Cache Side Channels in SGX Enclaves and Cryptographic APIs;Tuba;IEEE Transactions on Dependable and Secure Computing,2022
2. FUNDAE: Fault Template Attack on SUNDAE-GIFT AEAD Scheme
3. GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking
4. Theorem proof based gate level information flow tracking for hardware security verification
5. Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks
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