A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET
Author:
Affiliation:
1. Sony Semiconductor Solutions Corporation,Atsugi,Japan
2. imec,Leuven,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10405424/10405847/10405898.pdf?arnumber=10405898
Reference7 articles.
1. A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
2. A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS
3. Adaptive low-jitter LC-based clock distribution
4. Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
5. A Clock Distribution Scheme Insensitive to Supply Voltage Drift with Self-Adjustment of Clock Buffer Delay
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