Author:
Chakraborty Avijit,Walker D.M.H.
Funder
National Science Foundation
Cited by
3 articles.
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2. Path Unselection for Path Delay Fault Test Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
3. Topological Heuristics for Scan Test Overhead Reduction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022