Author:
Gimenez Gregoire,Cherkaoui Abdelkarim,Cogniard Guillaume,Fesquet Laurent
Cited by
21 articles.
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1. An Efficient Design Flow for Iterative Asynchronous Bundled-Data Circuits on FPGA;2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV);2024-06-06
2. An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
3. Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators;Lecture Notes in Computer Science;2024
4. Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024
5. Method for Data-Driven Pruning in Micropipeline Circuits;2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC);2023-10-16