Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation
Author:
Affiliation:
1. Indian Institute of Technology Roorkee,Department of Electronic and Communication Engineering,Roorkee,India
2. PDPM IIITDM Jabalpur,Department of Electronic and Communication Engineering,Jabalpur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117590/10117577/10117789.pdf?arnumber=10117789
Reference15 articles.
1. Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques;jaisawal;journal of lOP Science Semicond Sci Technol,2022
2. A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits
3. A comprehensive review on microwave FinFET modeling for progressing beyond the state of art
4. A 14nm logic technology featuring 2nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588 ?m2 sram cell size;natarajan;2014 IEEE International Electron Devices Meeting,0
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