Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip-Reference-Cited by-同舟云学术

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Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip

Published:2016-07 Issue: Volume: Page:
ISSN:
Container-title:2016 28th Euromicro Conference on Real-Time Systems (ECRTS)
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Author:

Abdallah Laure,Jan Mathieu,Ermont Jerome,Fraboul Christian

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7557819/7557852/07557871.pdf?arnumber=7557871

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Timing-accurate scheduling and allocation for parallel I/O operations in real-time systems;Journal of Systems Architecture;2024-07

2. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks;The Journal of Supercomputing;2024-06-23

3. Integrated Energy Control for Hard Real-Time Networks-on-Chip;2019 IEEE Real-Time Systems Symposium (RTSS);2019-12

4. Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation;Real-Time Systems;2019-03-06

5. Safe and efficient power management of hard real-time networks-on-chip;Integration;2019-03

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