Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications
Author:
Affiliation:
1. ABV-Indian Institute of Information Technalogy & Management,Gwalior,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117603/10119237/10119339.pdf?arnumber=10119339
Reference20 articles.
1. A Noise-Efficient 36 nV/ $\surd $ Hz Chopper Amplifier Using an Inverter-Based 0.2-V Supply Input Stage
2. A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM
3. A novel method of wideband acquisition and anti-sideband lock in PM receivers using FFT
4. A Novel scheme of High-Speed Phase-Frequency Detector for Low-Power Low-Phase noise PLL Design
5. Phase locked loop using sub harmonic injection technique with auto adjusted delay locked loop;patel;ICTACT Journal on Microelectronics,2020
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology;2024 IEEE International Conference on Applied Electronics and Engineering (ICAEE);2024-07-27
2. Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application;Journal of Electronic Testing;2024-04
3. Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology;Journal of The Institution of Engineers (India): Series B;2024-01-22
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