Demonstration on Warpage Estimation Approach Utilized in Fan-Out Panel-Level Packaging Enabled by Multi-Scale Process-Oriented Simulation
Author:
Affiliation:
1. National Tsing Hua University,Department of Power Mechanical Engineering,Hsinchu,Taiwan,R.O.C,30013
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10118246.pdf?arnumber=10118246
Reference12 articles.
1. Improved Approaches for FEA Analyses of PBGA Packages Subjected to Thermal Cycling
2. Comparison of Mechanical Modeling to Warpage Estimation of RDL-First Fan-Out Panel-Level Packaging
3. Simulation methodology development of warpage estimation for epoxy molding compound under considerations of stress relaxation characteristics and curing conditions applied in semiconductor packaging
4. Analysis of thermal cycling testing for a 3D integrated package with inter-chip microbumps
5. The Redistribution Layer-First Embedded Fan-Out Wafer Level Packaging for 2-D Ultrasonic Transducer Arrays
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