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3-D Topologies for Networks-on-Chip

Published:2007-10 Issue:10 Volume:15 Page:1081-1090
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Pavlidis Vasilis F.,Friedman Eby G.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4303116/04303130.pdf?arnumber=4303130

Cited by 215 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. A survey on mapping and scheduling techniques for 3D Network-on-chip;Journal of Systems Architecture;2024-02

3. Evaluation of 3D-DiamondMesh Homogeneous and Heterogeneous Architectures;TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON);2023-10-31

4. Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey;ACM Transactions on Design Automation of Electronic Systems;2023-10-30

5. Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures;ACM Journal on Emerging Technologies in Computing Systems;2023-06-30

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