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Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

  • Published:2010-03 Issue:3 Volume:18 Page:410-422
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kuang Weidong,Zhao Peiyi,Yuan J. S.,DeMara R. F.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits;Journal of Low Power Electronics and Applications;2024-01-14

2. ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16

3. Error Resilient Sleep Convention Logic Asynchronous Circuit Design;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

4. Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23

5. Identification and Confinement of Fault Sensitivity Windows in QDI Logic;2020 Austrochip Workshop on Microelectronics (Austrochip);2020-10-07
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