Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic-Reference-Cited by-同舟云学术

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Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic

Published:2002-10 Issue:5 Volume:10 Page:532-541
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Seong-Ook Jung ,Ki-Wook Kim ,Sung-Mo Kang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/26463/01178076.pdf?arnumber=1178076

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits;ETRI Journal;2019-04

2. Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates;Integration;2012-01

3. General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-07

4. A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates;IEICE Transactions on Electronics;2009

5. NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME;Journal of Circuits, Systems and Computers;2007-02

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