Dynamic Built-In Redundancy Analysis for Memory Repair

Author:

Lee HayoungORCID,Han Donghyun,Lee Seungtaek,Kang SunghoORCID

Funder

Ministry of Trade, Industry and Energy

KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Efficient Built in Self Repair for Multiple RAMs;2023 IEEE 8th International Conference for Convergence in Technology (I2CT);2023-04-07

3. VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM;Integration;2022-11

4. Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM;Micromachines;2022-06-19

5. ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-06

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