A Low Error and High Performance Multiplexer-Based Truncated Multiplier-Reference-Cited by-同舟云学术

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A Low Error and High Performance Multiplexer-Based Truncated Multiplier

Published:2010-12 Issue:12 Volume:18 Page:1767-1771
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chang Chip-Hong,Satzoda Ravi Kumar

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5634429/05256136.pdf?arnumber=5256136

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Generalized Power Reduction Technique for Truncated Multiplier via Latching the Data Inputs and Error Compensating Carry;Iranian Journal of Science and Technology, Transactions of Electrical Engineering;2023-09-14

2. A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation;2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2022-11-11

3. Designing Energy-Efficient Approximate Multipliers;Journal of Low Power Electronics and Applications;2022-09-27

4. Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing;Computer Systems Science and Engineering;2022

5. An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation;Electronics;2021-10-15

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