FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7438527/7443105/07443745.pdf?arnumber=7443745
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration;2024 International Telecommunications Conference (ITC-Egypt);2024-07-22
2. A Novel Approach to AES S-BOX and Inverse S-BOX Design on FPGA Devices;2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2023-12-18
3. Hybrid model of image security using steganography and symmetric cryptography techniques;RECENT ADVANCES IN SCIENCES, ENGINEERING, INFORMATION TECHNOLOGY & MANAGEMENT;2023
4. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-09
5. 90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate;International Journal of e-Collaboration;2022-05-06
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