Author:
Nagaraj S.,Reddy G.M. Sreerama,Mastani S. Aruna
Cited by
8 articles.
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1. Design and Implementation of 8-Bit Vedic Multiplier Using Cadence 45nm Technology;2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2024-01-11
2. A Way to Optimize Delay of Carry-Skip Adders by Using Blocks of Variable Sizes;Highlights in Science, Engineering and Technology;2023-11-28
3. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
4. An Improved switching activity optimised LFSR for energy efficient BIST applications;2023 2nd International Conference on Vision Towards Emerging Trends in Communication and Networking Technologies (ViTECoN);2023-05-05
5. Certain Investigations on Adder Design for VLSI Signal Processing;2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS);2022-03-25