A 22nm FD-SOI CMOS 2-way D-band Power Amplifier Achieving PAE of 7.7% at 9.6dBm OP1dB and 3.1% at 6dB Back-off by Leveraging Adaptive Back-Gate Bias Technique-Reference-Cited by-同舟云学术

A 22nm FD-SOI CMOS 2-way D-band Power Amplifier Achieving PAE of 7.7% at 9.6dBm OP1dB and 3.1% at 6dB Back-off by Leveraging Adaptive Back-Gate Bias Technique

Published:2022-06-19 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Author:

Rahimi Elham¹,Bozorgi Farhad²,Hueber Gernot³

Affiliation:

1. Keysight Technologies,Germany

2. Barkhausen Institut,Germany

3. Silicon Austria Labs,Austria

Funder

Styrian Business Promotion Agency (SFG)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9862947/9862948/09863164.pdf?arnumber=9863164

Reference8 articles.

1. A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines;seo;2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers,0

2. 24.7 A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS

3. A 140 GHz T/R Front-End Module in 22 nm FD-SOI CMOS

4. Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies

5. A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators

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