Experimental Investigation of Dual-Gate LDMOS for Low On-Resistance
Author:
Affiliation:
1. Southeast University,National Asic System Engineering Reserch Center, School of Electronic Science & Engineering,Nanjing,China
2. CSMC Technologies Corporation,Wuxi,China
Funder
National Natural Science Foundation of China
Southeast University
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9813543/9813532/09813673.pdf?arnumber=9813673
Reference12 articles.
1. Schottky Soutce LDMOS – Electrical SOA Improvement Through BJT Suppression;toner;ISPSD 2020,0
2. Figure-of-Merit for Laterally Diffused MOSFETs with Rectangular and Semi-Circular Field Oxides
3. Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance
4. 100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance
5. Significant On-Resistance Reduction of LDMOS Devices by Intermitted Trench Gates Integration
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A High-Performance and Low HCI Degradation LDMOS Device With a Hybrid Field Plate;IEEE Journal of the Electron Devices Society;2024
2. Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect;Engineering Research Express;2023-08-29
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