Investigation on Low Power Digital Tree Multipliers

Abstract

VLSI is the relating to more than one branch of science of utilizing the advanced semiconductor technology to develop various functional units of computational System. The most complex function carried out by ALU is multiplication. Digital multiplication is most extensively used operation particularly in signal processing, System designer has to sacrifice silicon die area in order to make the multiplication as soon as possible. In this paper, various multiplier architectures are simulated and compared with high speed and low power 8x8 Vedic multiplier (Urdhva Triyagbhayam) which uses modified carry select adder for partial product reduction. The design is implementation and simulation has been done by Microwind tool with 90 nm technology. The simulation result shows 58% of power reduction, 65% of delay reduction and 44% of area reduction has been attained.