Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications

Author:

Thakur Rajiv Ranjan1,Chaturvedi Nidhi2

Affiliation:

1. CSIR-Central Electronics Engineering, Research Institute, Pilani 333031, India

2. Academy of Scientific and Innovative Research (AcSIR), Ghaziabad 201002, India

Abstract

In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text] tuning using metal contact length ([Formula: see text], (ii) threshold voltage ([Formula: see text] tuning using metal electrode work functions ([Formula: see text] and (iii) threshold voltage ([Formula: see text] tuning using metal contact width ([Formula: see text]. The device has an [Formula: see text]/[Formula: see text] ratio of 105, suppressed off-state leakage in the range of 10[Formula: see text]–10[Formula: see text]A. The simulation work has been carried out on a commercially available ATLAS device simulator from Silvaco.

Publisher

World Scientific Pub Co Pte Lt

Subject

Condensed Matter Physics,General Materials Science

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