A Low Offset Dynamic Comparator with Offset Elimination Circuit-Reference-Cited by-同舟云学术

A Low Offset Dynamic Comparator with Offset Elimination Circuit

Published:2017-03-17 Issue:07 Volume:26 Page:1750115
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

Huang Cheng¹,Lin Zhilun¹,Wu Jianhui¹,Chen Chao¹

Affiliation:

1. National ASIC System Engineering Center, Southeast University, Sipailou#2, Nanjing, Jiangsu, China

Abstract

A new dynamic comparator with offset elimination circuit is proposed. The offset elimination circuit decreases the influence of the offset voltage effectively and increases the resolution of the comparator. The simulation results show that, if the pre-set offset voltage is 10[Formula: see text]mV, the offset elimination circuit can decrease to the enough low value, which meets the requirements of the system. The standard deviation of the offset voltage decreases from 7.27[Formula: see text]mV to 1.15[Formula: see text]mV with the utilization of the offset elimination circuit in Monte Carlo simulation.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126617501158

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