Power and Noise Reduction of High-Frequency Variable Gain Amplifier

Author:

Sajin C. S.1ORCID,Shahul Hameed T. A.2

Affiliation:

1. Department of ECE, LBS Centre for Science and Technology, Research Centre, University of Kerala, Thiruvananthapuram, Kerala, India

2. Department of ECE, TKM College of Engineering, Kollam, Kerala, India

Abstract

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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