Front-End Rectifier of Self-Compensation Matching with Parasitic Cancellation for Dual-Band RFID Tag

Author:

Liu Xianming123,Chang Yinghui4,Wu Weikang4,Zhou Zhixin5,Luo Hongyin5,Xiao Wenrun13,Huang Chao3,Guo Donghui136

Affiliation:

1. School of Electronic Science and Engineering, Xiamen University, 422 Xiang’an South Road, Xiamen, Fujian, P. R. China

2. School of Physics, Electronics and Intelligent Manufacturing, Key Laboratory of Intelligent Control Technology for Wuling-Mountain Ecological Agriculture in Hunan Province, Huaihua University, Huaihua, Hunan 418008, P. R. China

3. Ningbo Institute of Artificial Intelligence Industry, Ningbo, Zhejiang, P. R. China

4. Academy for Network and Communications of CETC, Shijiazhuang, Hebei 050299, P. R. China

5. Xiamen EMBEDEEP Technology Co., Ltd., Xiamen, Fujian, P. R. China

6. R&D Center for Integrated Circuit Engineering of Fujian Province, Xiamen, Fujian 361005, P. R. China

Abstract

This paper presents an innovative cross-coupled differential drive rectifier for dual-band Radio frequency identification (RFID) tags. A self-compensating rectifier with enhanced power-conversion efficiency (PCE) at low and high RF power is proposed. The proposed rectifier utilizes a self-compensating circuit, the extra two cross-couple transistors, to increase the gate voltage of transistors to control the conduction of the rectifying transistors. In order to adapt high frequency (HF) and ultrahigh frequency (UHF) rectification, the matching circuit is designed with parasitic cancellation technology. Moreover, the cascading power management circuits are added to generate a stable output voltage. The multi-standard rectifier is designed and simulated in [Formula: see text] CMOS process. The simulated result shows that the proposed three-stage rectifier achieves a PCE 74% (at [Formula: see text] load) when receiving a 915[Formula: see text]MHz signal with average power of [Formula: see text]. Moreover, the maximum efficiency achieves 56% at HF 13.56[Formula: see text]MHz, and the final output voltage can be stabilized at a specific voltage of 1.052[Formula: see text]V.

Funder

Key special projects of National Key R&D plan project

Publisher

World Scientific Pub Co Pte Ltd

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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