Multistage Latency Adders Architecture Employing Approximate Computing

Abstract

This paper proposed an energy efficient adder employing multistage latency and approximate computing technology. The delay of the adder decreases after the critical path of the adder is divided into multiple short stages with series of predictors, then the approximate computing technology is exploited to make a tradeoff between output quality and energy efficiency. The proposed design is applied into discrete cosine transformation (DCT) in image processing and support vector machine (SVM) algorithm in machine learning to verify its availability, the simulation results demonstrate that the proposed approximate adder provides 25.6% power-delay-product (PDP) reduction and 2 orders of magnitude reduction in output error than the recent counterpart designs. Compared with the conventional accurate ripple carry adder (RCA) and Kogge stone adde (KSA), the proposed design presents 66.5% to 37.6% PDP reduction, at the cost of negligible output quality reduction, which are qualified as peak signal-to-noise ratio (PSNR) for DCT (decreases from 33.88dB to 33.84dB) and classification accuracy for SVM (decreases from 80.46% to 79.19%).