An Efficient Double Deep Q Learning Network-Based Soft Faults Detection and Localization in Analog Circuits

Abstract

To identify whether the circuit under test is fault-free or faulty, fault diagnosis is conducted in an analog circuit. However, in the case of fault detection (FD) techniques, the size of FD is the main challenge in testing, especially for complex analog circuits. Hence to reduce the size of FD, specific test nodes are chosen to perform fault diagnosis from the available accessible test nodes. Specific test nodes are selected based on the faults classification efficiency of fault diagnosis. Therefore, this paper proposes an approach for single and multiple soft fault diagnosis using minimum test nodes in analog electronic circuits. The proposed double deep Q-learning-based hybrid Simulated annealing–Tabu search (DDQN-Hybrid SATS) technique determines minimum test nodes with the utilization of distance metric for fault classification. The DDQN-Hybrid SATS technique is used to identify minimum nodes for testing. In this, the double deep Q learning network (DDQN) ensures better reliability and faster convergence in learning but suffers from catastrophic forgetting issues. To prevent such issues, the DDQN approach is optimized using a hybrid SATS algorithm. The hybrid optimization of simulated annealing (SA) and Tabu search (TS) coalesce the advantages of individual optimization procedures to provide the optimum solution in a fast and effective way. The results for a fourth-order low pass filter are presented (i.e., first CUT) and an eight-bit digital to analog converter (i.e., second CUT). Moreover, the simulation experiment reveals that the proposed DDQN-Hybrid SATS technique achieves greater overall fault classification accuracy of about 96.25% than other compared techniques with minimum computation time.