FPGA-Based Pipelined Architecture for Real-Time Estimation of Sensitivity Maps Using Pre-Scan Method in Parallel MRI

Abstract

Parallel MRI (pMRI) is a widely used technique for increasing the MRI acquisition speed, by using multiple receiver coils with spatially discriminated sensitivities. Sensitivity encoding (SENSE) is a parallel MRI technique used for reconstructing the aliasing free images from the under-sampled MRI data using the spatial information obtained from multiple receiver coils. Precise receiver coil sensitivity estimation is critical for the correct image reconstruction from the under-sampled data in SENSE. Pre-scan method is a quick and conventionally used method for correct estimation of the receiver coil sensitivities, to be used in SENSE. In this work, an application-specific hardware implemented on FPGA (Field Programmable Gate Array) for real-time sensitivity maps estimation using the pre-scan method is proposed. The proposed architecture has the potential to be installed on the receiver coil data acquisition system, which would provide sensitivity maps for image reconstruction, without moving the raw data to the MRI workstation. Parallelism is utilized in the proposed pipelined architecture to make it even faster. From the experimental results, it is shown that the proposed architecture estimates the sensitivity maps in only 1.466[Formula: see text]ms for eight receiver coils. Furthermore, high mean SNR (30[Formula: see text][Formula: see text]dB), low root-mean-square-error ([Formula: see text]) and low artifact power ([Formula: see text]) are achieved for the under-sampled human head, cardiac and phantom data sets (acceleration factor = 2), reconstructed with SENSE algorithm utilizing the sensitivity maps estimated by the proposed architecture.