A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

Abstract

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.