Design and Development of N-Level Symmetrical Multilevel Inverter Topology with Reduced Switches

Abstract

In this paper, 11-level multilevel inverter with reduced power switch configuration is developed and investigated. This proposed configuration can be extended for [Formula: see text] levels with the required number of power switches. Comparative analysis between the proposed multilevel inverter topology and well-known existing multilevel inverter topologies is carried out. Fundamental switching angle calculation for the power switches of the proposed topology has been optimized using black widow optimization algorithm technique and also the proposed topology has been tested with the classical multicarrier alternative phase opposition disposition PWM technique. To test the effectiveness of the proposed topology, different tests have been conducted such as testing with different modulation indexes, DC input voltages, load settings and voltage ride-through capabilities. This paper presents various simulation and experimental results under various operating conditions to prove the performance of the proposed multilevel inverter topology.