Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs

Author:

Michail Harris E.1,Athanasiou George S.2,Kelefouras Vasileios I.2,Theodoridis George2,Stouraitis Thanos32,Goutis Costas E.2

Affiliation:

1. Electrical Engineering and Information Technology Department, Cyprus University of Technology, Lemesos 3036, Cyprus

2. VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras GR-26504, Greece

3. ECE Department, Khalifa University, PO Box 127788, Abu Dhabi, UAE

Abstract

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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