EXPLORATION OF SPATIAL-TEMPORAL DYNAMIC PHENOMENA IN A 32×32-CELL STORED PROGRAM TWO-LAYER CNN UNIVERSAL MACHINE CHIP PROTOTYPE

Author:

PETRÁS ISTVÁN1,REKECZKY CSABA1,ROSKA TAMÁS1,CARMONA RICARDO2,JIMÉNEZ-GARRIDO FRANCISCO2,RODRÍGUEZ-VÁZQUEZ ANGEL2

Affiliation:

1. Analogical and Neural Computing Laboratory, Computer and Automation Research Institute, Hungarian Academy of Sciences, Kende u.11, Budapest, 1111, Hungary

2. Instituto de Microelectrónica de Sevilla-CNM-CSIC, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain

Abstract

This paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and distributed image memory on a common silicon substrate. The chip was designed and fabricated in a standard 0.5 μm CMOS technology and contains approximately 500 000 transistors. It consists of 1024 processing units arranged into a 32×32 grid. Each processing element contains two coupled CNN cores, thus, constituting two parallel layers of 32×32 nodes. The functional features of the chip are in accordance with the 2nd Order Complex Cell CNN-UM architecture. It is composed of two CNN layers with programmable inter- and intra-layer connections between cells. Other features are: cellular, spatial-invariant array architecture; randomly selectable memory of instructions; random storage and retrieval of intermediate images. The chip is capable of completing algorithmic image processing tasks controlled by the user-selected stored instructions. The internal analog circuitry is designed to operate with 7-bits equivalent accuracy. The physical implementation of a CNN containing second order cells allows real-time experiments of complex dynamics and active wave phenomena. Such well-known phenomena from the reaction–diffusion equations are traveling waves, autowaves, and spiral-waves. All of these active waves are demonstrated on-chip. Moreover this chip was specifically designed to be suitable for the computation of biologically inspired retina models. These computational experiments have been carried out in a developmental environment designed for testing and programming the analogic (analog-and-logic) programmable array processors.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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