Chip-Level Substrate Coupling Analysis with Reference Structures for Verification-Reference-Cited by-同舟云学术

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Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Published:2007-12-01 Issue:12 Volume:E90-A Page:2651-2660
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Author:

KOSAKA D.,NAGATA M.,MURASAKA Y.,IWATA A.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits;IEEE Transactions on Components, Packaging and Manufacturing Technology;2014-06

2. Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate;IEICE Electronics Express;2014

3. Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components;IEICE Transactions on Electronics;2013

4. Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2012

5. On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors;IEICE Transactions on Electronics;2012

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