1. Ancona,~M G. and Tiersten,~H F.: Macroscopic physics of the silicon inversion layer, Phys. Rev., 35, 7959–7965, 1987.
2. Bai, P.: A 65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell, Intel Corporation, USA, in Techn. IEEE Int. Electron Devices Meeting, 2004.
3. Caroli,~C., Combescot,~R., Nozieres,~P., and Saint-James,~D.: A direct calculation of the tunnelling current II, free electron description, J. of Physics: Condensed Matter, 2598–2610, 1971.
4. Chau,~R., Doyle,~B., Doczy,~M., Datta,~S., Hareland,~S., Jin,~B., Kavalieros,~J., and Metz,~M.: A Silicon Nano-Transistors and Breaking the 10 nm Physical Gate Length Barrier, Components Research, Intel Corporation, USA, 2006.
5. Choi,~C.-H., Nam,~K.-Y., Yu,~Z., and Dutton,~R W.: Impact of gate direct tunneling current on circuit performance: A simulation study, IEEE Transactions on Elect. Devices, 48, 2823–2829, 2001.