Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

Author:

Neudeck Philip G.1,Spry David J.2,Lukco Dorothy1,Chen Liang Yu3

Affiliation:

1. NASA Glenn Research Center

2. NASA Glenn Research Center (GRS)

3. Ohio Aerospace Institute

Abstract

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

Publisher

Trans Tech Publications, Ltd.

Subject

Mechanical Engineering,Mechanics of Materials,General Materials Science

Reference7 articles.

1. J. Cressler and H.A. Mantooth, Extreme Environment Electronics, CRC Press, Boca Raton, 2013.

2. P. Neudeck et al., Proc. 2018 IMAPS Int. Conf. High Temperature Electronics, p.71.

3. P. Neudeck and D. Spry, Mat. Sci. Forum 1004 (2020) 1057.

4. D. Spry et al., Mat. Sci Forum 828 (2016) 1112.

5. R.F. Pierret, Field Effect Devices, in Modular Series on Solid State Devices, Vol. 4, Addison-Wesley, Reading MA, 1983.

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