Abstract
Nanosheet-based transistor architectures for advanced CMOS have sophisticated 3D geometries and aggressively scaled dimensions imposing new challenges to wet etch and gas phase etch. In this paper, we describe three nanosheet-based transistor architectures (nanosheet, forksheet, and CFET) as well as associated challenges for wet etch and gas phase etch at various stages of the process flow, including channel release, work function metal patterning, and controlled dielectric etchback for stacked source-drain formation. The compatibility of etch processes with confined spaces and high-aspect-ratio structures becomes increasingly important for novel nanosheet-based transistor architectures.
Publisher
Trans Tech Publications, Ltd.
Subject
Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics
Reference10 articles.
1. C. Auth et al., A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors, 2012 IEEE Symposium on VLSI Technology, 2012, pp.131-2.
2. Information on: news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture, June 2022.
3. Information on: https://www.intel.com/content/www/us/en/silicon-innovations/6-pillars/process.html, July 2021.
4. Information on: https://pr.tsmc.com/english/news/3021, April 2023.
5. J. Jeong et al., World's First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFETTM) Process, 2023 IEEE Symposium on VLSI Technology, 2023, pp.158-159.