Demonstration of Low Interface Trap Density (~3×10¹¹eV^-1cm^-2) SiC/SiO₂ MOS Capacitor with Excellent Performance Using H₂+NO POA Treatment for SiC Power Devices

Abstract

In this work, we report on the engineering of the SiC/SiO2 MOS interface using H2 treatments along with NO POA to improve the interface characteristics and device reliability. Significantly low Dit of 3×1011 eV-1cm-2, stable threshold voltage, and long gate oxide lifetime > 105 s have been achieved by H2 annealing before NO POA of thermal SiO2. Through device electrical characterization and material analysis, we show that the performance enhancement is due to the reduction of interface defects and trapped charges in the SiO2 surface layer after the POA treatment, which in turn, significantly suppresses the threshold voltage instability.