Rearrangement of Surface Structure of 4o Off-Axis 4H-SiC (0001) Epitaxial Wafer by High Temperature Annealing in Si/Ar Ambient

Abstract

Mechanism of surface roughening caused by the polishing induced subsurface damage on 4o off-cut 4H-SiC (0001) substrate during thermal etching, CVD epitaxial growth, and the subsequent high temperature annealing was investigated in the wide temperature range of 1000-1800°C. Different from the previous study based on a macroscopic characterization by optical microscopy, microscopic characterization based on a scanning electron microscopy (SEM) was employed in this study. By utilizing the SEM operated under various conditions, disordered step arrangements as well as stacking faults and dislocations were imaged. The obtained results revealed that the SFs cause the fluctuation in the step kinetics, resulting in the step bunching formation during the thermal process.