Impact of the Gate Material on the Deep Levels in a-Si:H/c-Si Metal-Insulator-Semiconductor Capacitors

Abstract

Deep Level Transient Spectroscopy (DLTS) has been applied to Metal-Insulator-Semiconductor (MIS) capacitors, consisting of a p+ or n+ a-Si:H gate on an intrinsic i-a-Si:H passivation layer deposited on crystalline silicon n-or p-type substrates. It is shown that the type of gate has a pronounced impact on the obtained spectra, whereby both the kind of defects (dangling bonds at the a-Si:H/(100) c-Si interface (Pb0 defects) or in the amorphous silicon layer (D defects) and their relative importance (peak amplitude) may be varied. The highest trap densities have been found for the p+ a-Si:H gate capacitors on an n-type Si substrate. In addition, the spectra may exhibit unexpected negative peaks, suggesting minority carrier capture. These features are tentatively associated with interface states at the p+ or n+ a-Si:H/i-a-Si:H interface. Their absence in Al-gate capacitors is in support of this hypothesis.