Improvement of Quality of Thick 4H-SiC Epilayers

Abstract

The epitaxial growth of ~250 μm thick 4H-SiC epilayers has been demanded for ultra-high-voltage power devices. We have attempted to improve the quality of thick epilayers. At the edge of wafer, stacking faults, epi-crown and interfacial dislocations could be well suppressed by controlling the distribution of growth rate. Investigation of carrier concentration depth profile revealed that increasing surface roughness increased the carrier concentration during thick epitaxial growth. Under N2-doped growth condition, memory effect by accumulation of by-products containing dopant element is also one of the reasons of the carrier concentration increasing during the growth.