Affiliation:
1. Bangladesh University of Engineering and Technology
Abstract
The performance and characteristics of Double Gate MOSFET with high dielectric constant (high-κ) gate stack have been analyzed and compared with those of conventional pure SiO2 gate MOSFET. Quantum Ballistic Transport Model has been used to demonstrate the performance of the device in terms of threshold voltage, drain current in both low and high drain voltage regions and subthreshold swing. The effect of temperature on the threshold voltage and subthreshold characteristics has also been observed. This work reveals that improved performance of this structure can be achieved by scaling the gate length and illustrates its superiority over SiO2 gate MOSFETs in achieving long-term ITRS goals.
Publisher
Trans Tech Publications, Ltd.
Reference12 articles.
1. The International Technology Roadmap for Semicoductors. (2008). Available: www. itrs. net/links/2008ITRS/Home2008. htm.
2. H. Iwai, Roadmap for 22 nm and beyond, in Microelectronic Engineering, in press (Elsevier), March, (2009).
3. M. K. Ashraf, A. I. Khan and A. Haque, Wave function penetration effects on ballistic drain current in double gate MOSFETs fabricated on <100> and <110> silicon surfaces, in Solid-State Electronics., vol. 53, no. 3, p.271–275, (2009).
4. M. S. Lundstrom, K. D. Cantley, H. S. Pal, Nanoscale transistors: Physics and materials, in Materials Research Society Symposim Proc., vol. 958, (2007).
5. S. Hasan, J. Wang and M. Lundstrom, Device design and manufacturing issues for 10 nm-scale MOSFETs: a computational study, in Solid-State Electronics, vol. 48, p.867–875, (2004).
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