SiC MOSFET with a Self-Aligned Channel Defined by Shallow Source-JFET Implantation: A Simulation Study

Abstract

A new concept for SiC MOSFET with a self-aligned channel is presented. The channel is defined by shallow source-JFET implantation into a counter-doped layer. This concept is verified by TCAD device simulations. It is shown that the method is applicable to fabrication of functional devices. The most critical parameter of the process is misalignment between channel and p-shield. Almost no change of electrical current in forward conduction state and the leakage current and electric field in the gate oxide in blocking state is observed for the misalignments below 400 nm.