Modelling and Simulation of Hetero-Dielectric Surrounding Gate TFET

Abstract

Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influence of short channel effects and the leakage current, a surrounding gate with three different work function materials is used. Stacked dielectric or hetero-dielectric is used to improve the ON current of device. Performance of the device has been analyzed with different gate material lengths such as 10 nm, 15 nm and 20 nm. The developed 2-D mathematical model is used to obtain results like drain current, surface potential and electrical field in the vertical and lateral direction. From the results, a reduction in the device limitations is inferred and the leakage current is also considerably reduced. It has been found from the presented results that the proposed device structure Tri Material Cylindrical Gate Tunnel FET (TM CG TFET) provides the improved ON state current (10-3A/µm) and reduced OFF state current (10-14A/µm). The accuracy of the results and characteristics of the device are evaluated using TCAD simulations.