Challenges and Solutions for Fabricating Isolation Trenches for High Aspect Ratio Sensors

Abstract

A CMOS compatible integrated MEMS process for fabricating differential capacitance based sensor on SOI wafer is presented. High aspect ratio features are etched in the device layer of SOI wafer and are electrically isolated from each other and circuit elements except where interconnection is required using isolation trenches. The Isolation trenches are first etched on device Si to electrically isolate static combs while maintain the mechanical connection. This scheme results in high sense capacitance with increased SNR. Various considerations which need to be addressed for fabricating the isolation trenches are presented in this paper and the results using the example of an accelerometer are presented. Various isolation trench ends are designed and fabricated and the results are discussed.