Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET

Author:

Usha C.1,Vimala Palanichamy1

Affiliation:

1. Dayananda Sagar College of Engineering

Abstract

In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.

Publisher

Trans Tech Publications, Ltd.

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