Two novel PSRR enhancement techniques for voltage reference of depletion NMOS-Reference-Cited by-同舟云学术

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Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

Published:2022-04-25 Issue:8 Volume:19 Page:20220009-20220009
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Song Boqi¹,Chai Changchun¹,Li Fuxing¹,Jiang Chanrong¹,Yang Yintang¹

Affiliation:

1. Key Laboratory of Ministry of Education for Wide BandGap Semiconductor Materials and Devices, School of Microelectronics, Xidian University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/8/19_19.20220009/_pdf

Reference30 articles.

1. [1] P.E. Allen and D.R. Holberg: CMOS Analog Circuits Design (Oxford University Press, 2000) 2nd ed.

2. [2] B. Razavi: Design of Analog CMOS Integrated Circuits (McGraw-Hill, New York, 2000).

3. [3] M. Chahardori, et al.: “A sub 1V high PSRR CMOS bandgap voltage reference,” Microelectronics Journal 42 (2011) 1057 (DOI: 10.1016/j.mejo.2011.06.010).

4. [4] J. Wu, et al.: “A high PSRR CMOS voltage reference with 1.2V operation,” Analog Integr. Circuits Signal Process 77 (2013) 79 (DOI: 10.1007/s10470-013-0122-y).

5. [5] Y.-B. Gu, et al.: “CMOS voltage reference with multiple outputs,” IET Circuits Devices Syst. 2 (2008) 222 (DOI: 10.1049/iet-cds:20070211).

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