Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity-Reference-Cited by-同舟云学术

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Published:2017 Issue:23 Volume:14 Page:20171017-20171017
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Kogo Kenji¹,Norimatsu Takayasu¹,Kohmu Norihiro¹,Kawamoto Takashi¹

Affiliation:

1. Research & Development Group, Hitachi Ltd.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/23/14_14.20171017/_pdf

Reference11 articles.

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2. [2] T. Kawamoto, et al.: “Multi-standard 185 fsrms 0.3-to-28 Gb/s 40 dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28 nm CMOS,” ISSCC Dig. Tech. Papers (2015) 54 (DOI: 10.1109/ISSCC.2015.7062922).

3. [3] M. Chandana, et al.: “Power integrity analysis for high performance design,” 2015 ICCEREC (2015) 48 (DOI: 10.1109/ICCEREC.2015.7337052).

4. [4] K. Kogo, et al.: “Power signal integrity for 25 Gbps 40 dB compensation signal conditioner for backplane architecture,” 2015ICSJ (2015) 212 (DOI: 10.1109/ICSJ.2015.7357400).

5. [5] W. Li-xin, et al.: “Power integrity analysis for high-speed PCB,” 2010 First International Conference on Pervasive Computing, Signal Processing and Applications (2010) 414 (DOI: 10.1109/PCSPA.2010.106).