A radiation harden enhanced Quatro (RHEQ) SRAM cell
Author:
Affiliation:
1. School of Electronics and Information Engineering, Anhui University
2. Industry Development and Promotion Center, Ministry of Industry and Information Technology of the Peoples Republic China
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/18/14_14.20170784/_pdf
Reference16 articles.
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2. [2] P. E. Dodd and L. W. Massengill: “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Trans. Nucl. Sci. 50 (2003) 583 (DOI: 10.1109/TNS.2003.813129).
3. [3] C. Qiet al.: “A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets,” IEEE Trans. Device Mater. Rel. 16 (2016) 388 (DOI: 10.1109/TDMR.2016.2593590).
4. [4] S. M. Jahinuzzamanet al.: “A soft error tolerant 10T SRAM bit-cell with differential read capability,” IEEE Trans. Nucl. Sci. 56 (2009) 3768 (DOI: 10.1109/TNS.2009.2032090).
5. [5] T. Calinet al.: “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nucl. Sci. 43 (1996) 2874 (DOI: 10.1109/23.556880).
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