A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Author:

PARK Dongchul1,DEBNATH Biplob1,DU David H.C.2

Affiliation:

1. University of Minnesota-Twin Cities

2. Computer Science and Engineering, the University of Minnesota-Twin Cities

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference27 articles.

1. [1] X. Jimenez, D. Novo, and P. Ienne, “Wear unleveling: Improving NAND flash lifetime by balancing page endurance,” FAST, 2014.

2. [2] J. Jeong, S.S. Hahn, S. Lee, and J. Kim, “Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling,” FAST, 2014.

3. [3] S. Lee, T. Kim, K. Kim, and J. Kim, “Lifetime management of flash-based SSDS using recovery-aware dynamic throttling,” FAST, 2012.

4. [4] K. Bang, K.-I. Im, D.-G. Kim, S.-H. Park, and E.-Y. Chung, “Power Failure Protection Scheme for Reliable High-Performance Solid State Disks,” IEICE Transactions on Information and Systems, vol.E96-D, no.5, pp.1078-1085, 2013.

5. [5] Samsung, “Why SSDs are Awesome: An SSD Primer,” tech. rep., Samsung Electronics, 2014.

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