A Machine Learning-Based Approach for Selecting SpMV Kernels and Matrix Storage Formats
Author:
Affiliation:
1. Graduate School of Information Sciences, Tohoku University
2. Information Systems Architecture Science Research Division, National Institute of Informatics
3. Cyberscience Center, Tohoku University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Link
https://www.jstage.jst.go.jp/article/transinf/E101.D/9/E101.D_2017EDP7176/_pdf
Reference33 articles.
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3. [3] W. Abu-Sufah and A.A. Karim, “Auto-tuning of sparse matrix-vector multiplication on graphics processors,” Supercomputing, Lecture Notes in Computer Science, vol.7905, pp.151-164, Springer Berlin Heidelberg, Berlin, Heidelberg, 2013. 10.1007/978-3-642-38750-0_12
4. [4] N. Bell and M. Garland, “Implementing sparse matrix-vector multiplication on throughput-oriented processors,” Proc. Conference on High Performance Computing Networking, Storage and Analysis, Article No. 18, Nov. 2009. 10.1145/1654059.1654078
5. [5] S. Bhowmick, V. Eijkhout, Y. Freund, E. Fuentes, and D. Keyes, “Application of machine learning in selecting sparse linear solvers,” International Journal of High Performance Computing Applications, 2006 (submitted).
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